1. Field of the Invention
The present invention relates to a device and a method for generating circuit connection information containing parasitic elements extracted from layout pattern data.
2. Description of the Background Art
FIG. 27 illustrates a first example of the conventional procedure for generating circuit connection information. Referring to FIG. 27, parameter data 302 such as capacitances of capacitors and transistor configurations is outputted from layout pattern data 110 in a parameter extracting process 301. In a manual circuit connection information generating process 303, the contents of the parameter data 302 are processed and first circuit connection information 112 is outputted. Then, a circuit simulation executing process 310 is carried out.
FIG. 28 illustrates a second example of the conventional procedure for generating circuit connection information. Referring to FIG. 28, the parameter data 302 such as capacitances of capacitors and transistor configurations is outputted from the layout pattern data 110 in the parameter extracting process 301. In the manual circuit connection information generating process 303, the contents of the parameter data 302 are processed and the first circuit connection information 112 is outputted.
After a parasitic element selecting process 304 is manually carried out, a manual adding process 305 to a circuit drawing provides a circuit drawing 120 including parasitic elements added to a normal circuit drawing.
Then, second circuit connection information 122 is extracted from the circuit drawing 102 in a circuit connection information extracting process 306, and the circuit simulation executing process 310 is carried out.
In this manner, the first example has extracted the circuit connection information containing the parasitic elements from the layout pattern data and then performed the circuit simulation and the like upon the circuit connection information. The second example has manually added the parasitic elements extracted from the layout pattern data onto the circuit drawing, extracted the circuit connection information containing the parasitic elements from the circuit drawing, and then performed the circuit simulation and the like.
To obtain circuit connection information containing the parasitic elements, the circuit connection information has been directly extracted from the layout pattern data, as in the first example of FIG. 27. However, this circuit connection information has been disadvantageous in that a node at which a waveform is desired to be observed is not specified from the circuit drawing when the circuit simulation is executed on the circuit connection information, causing difficulties in specifying defective portions in the circuit from the result of the circuit simulation.
The addition of the parasitic elements to the circuit drawing has been made inconveniently by hand as in the second example illustrated in FIG. 28, resulting in a prolonged period of design time.
In particular, insertion of the parasitic elements such as resistances in the circuit drawing has required division of one signal line by new nodes, sometimes requiring a great change in the circuit drawing with difficulty.
Further, if a circuit portion includes logically identical but physically different transistor connections between the circuit drawing and the layout pattern data, the parasitic elements extracted from the layout pattern data have not correctly been added directly to the circuit drawing.